Phase-locked loops (PLLs) are commonly used to generate an output signal having a particular oscillation frequency based on the frequency of an input reference signal by locking the phase of the output signal with the phase of the input reference signal. However, as the frequency of the input reference signal increases (e.g., frequencies in the GHz range or higher), the latencies and/or response times of the analog circuitry impair the ability of the analog PLLs to effectively lock the output signal with the input reference signal. Digital PLLs, on the other hand, suffer from inherent jitter (idle jitter or dither jitter), and there is a tradeoff between the tracking bandwidth and the inherent jitter of the digital PLL.